This invention relates to a digital to analog converter for converting a multi bit digital input signal into an analog output signal. The converter comprises an array of substantially equal conversion elements on a semiconductor chip and conversion element selection logic for selecting, in response to the multi bit digital input signal, from said array of conversion elements a number of signal-conversion elements for connection to an output terminal, the selection logic being adapted to perform a dynamic element matching algorithm for shaping the noise, caused by the inequalities of the conversion elements, to higher frequencies. A digital to analog converter of this kind is, for example, known from the article: xe2x80x9cLinearity Enhancement of Multibit Delta Sigma A/D and D/A Converters Using Data Weighted Averagingxe2x80x9d by R. T. Baird and T. S. Fiez in IEEE Transactions on Circuits and Systems-II: analog and digital signal processing, Vol. 42, No. 12, pp. 753-762, December 1995.
In many cases, such as video or high resolution audio, the use of multi bit analog to digital converters is preferred over single-bit converters. The quantization-noise level of the multi bit quantizers is inherently lower than that of single-bit quantizers (the theoretical signal to noise ratio of the system improves by approximately 6 dB per bit). Moreover, multi bit converters also have the advantage of being less sensitive to sample-clock jitter and intersymbol interference.
The improvement of the dynamic range of multi bit converters however only comes at the cost of severe linearity problems. When the value of the conversion elements is not exactly equal, the quantization levels are not exactly equidistant, the converter is non-linear and severe harmonic distortion in the output signal is generated. It is well known in the art, e.g. from the U.S. Pat. Nos. 3,982,172 and 4,703,310 of R. J. van de Plassche, to improve the linearity of multi bit converters by techniques of dynamic element matching. These techniques do not rely on analog accuracies and are therefore often preferred in modern IC processes. Although, of course, for converting a certain value of the digital input signal, the corresponding number of conversion elements is selected, the technique of dynamic element matching seeks to avoid that for each conversion the same conversion elements are selected. Therefore dynamic element matching decorrelates the mismatch errors of the conversion elements from the input signal, thereby reducing non-linear distortion, i.e. the generation of higher harmonics in the analog output signal. Some special kinds of dynamic element matching do not only decorrelate the mismatch errors from the input signal, but additionally xe2x80x9cshapexe2x80x9d the noise, caused by the inequalities of the conversion elements, out of the frequency band of interest. A simple and preferred method of dynamic element matching, belonging to this latter category, is the Data Weighted Averaging (DWA) algorithm, which is described in the above referenced article. In this algorithm, for each conversion the next K unit elements are used, K being the number of elements to be selected. In this way, a cyclic assignment of conversion elements is obtained, so that the error that is caused by the mismatch, is averaged much faster and thus the mismatch error becomes a high-frequency error by first-order shaping.
Although the above described known method of dynamic element matching shapes the noise to higher frequencies and thereby increases the signal to noise ratio of the analog to digital converter, the present invention recognizes that still better noise shaping and consequently further improved signal to noise ratio can be obtained. The analog to digital converter of the present invention is therefore characterized in that the selection by the dynamic element matching algorithm is adapted to the position of the conversion elements in said array so as to improve the shaping to higher frequencies of the noise caused by the systematic inequalities of the conversion elements.
The present invention is based on the per se known recognition that in IC implementation the errors of the conversion elements have almost always a random part and a systematic part. The systematic errors are caused by the occurrence of all kinds of gradients and variations during the manufacturing process of the integrated circuit, such as temperature gradients, doping concentration gradients, oxide thickness gradients and misalignment of masks. The invention recognizes that the course of the systematic errors of the conversion elements is predictable, that a better shaping of individual errors is obtained when a positive error (with respect to the mean value of the elements) is quickly compensated by a negative error of comparable magnitude and that, consequently, the dynamic matching algorithm can be adapted to optimize the shaping to higher frequencies of the mismatch noise which is caused by the systematic errors.
In most cases the conversion elements are arranged on the semiconductor chip in a row. In those cases often a linear gradient in the values of the individual elements is observed. Therefore, in those cases where at least part of the conversion elements is situated in a linear array of conversion elements, the analog to digital converter of the invention may be characterized in that the selection logic is arranged to select at least the majority of the conversion elements of the linear array in pairs of two conversion elements which lie in different halves of the linear array. More particularly, such digital to analog converter may be characterized in that the two conversion elements of each of said pairs lie substantially symmetrically with respect to the centre of the linear array.
Apart from selecting the conversion elements in pairs of two elements lying on both sides of the centre of the linear array and more particularly lying symmetrically with respect to the centre of the array, a further improvement may likely be obtained in case of lower oversampling ratios, by properly choosing the succession in which the pairs are selected and therefore the digital to analog converter of the invention may be further characterized in that the said pairs of conversion elements are successively selected so that in each half of the linear array every second element is selected in one direction and subsequently every second of the elements lying there between is selected in the opposite direction. A digital to analog converter with a slightly different selection algorithm may be characterized in that the second element of a pair and the element lying between the first element of said pair and the first element of the next pair, lie symmetrically with respect to the centre of the linear array.